CVE-2025-63384

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Source
https://cve.org/CVERecord?id=CVE-2025-63384
Import Source
https://storage.googleapis.com/cve-osv-conversion/osv-output/CVE-2025-63384.json
JSON Data
https://api.osv.dev/v1/vulns/CVE-2025-63384
Published
2025-11-10T20:15:49.013Z
Modified
2026-04-10T05:34:53.066963Z
Severity
  • 6.5 (Medium) CVSS_V3 - CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N CVSS Calculator
Summary
[none]
Details

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

References

Affected packages

Git / github.com/chipsalliance/rocket-chip

Affected ranges

Type
GIT
Repo
https://github.com/chipsalliance/rocket-chip
Events
Introduced
0 Unknown introduced commit / All previous commits are affected
Last affected
44b0b8249279d25bd75ea693b725d9ff1b96e2ab
Database specific 
{
    "versions": [
        {
            "introduced": "0"
        },
        {
            "last_affected": "1.6"
        }
    ]
}

Affected versions

v1.*
v1.6

Database specific

source 
"https://storage.googleapis.com/cve-osv-conversion/osv-output/CVE-2025-63384.json"