CVE-2025-63384

See a problem?
Please try reporting it to the source first.

Source

https://cve.org/CVERecord?id=CVE-2025-63384

Import Source

https://storage.googleapis.com/cve-osv-conversion/osv-output/CVE-2025-63384.json

JSON Data

https://api.osv.dev/v1/vulns/CVE-2025-63384

Published

2025-11-10T00:00:00Z

Modified

2026-08-12T03:51:37.680130191Z

Severity

6.5 (Medium) CVSS_V3 - CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N CVSS Calculator

Summary

[none]

Details

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

Database specific

{
    "osv_generated_from": "https://github.com/CVEProject/cvelistV5/tree/main/cves/2025/63xxx/CVE-2025-63384.json",
    "cna_assigner": "mitre"
}

References

Affected packages

Git / github.com/chipsalliance/rocket-chip

Affected ranges

Type

GIT

Repo

https://github.com/chipsalliance/rocket-chip

Events

Introduced

Last affected

44b0b8249279d25bd75ea693b725d9ff1b96e2ab

Database specific

Show details

{
    "cpe": "cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:*",
    "source": "CPE_RANGE",
    "extracted_events": [
        {
            "introduced": "0"
        },
        {
            "last_affected": "1.6"
        }
    ]
}

Affected versions

v1.*

v1.6

Database specific

source

"https://storage.googleapis.com/cve-osv-conversion/osv-output/CVE-2025-63384.json"