CVE-2026-72409

In the Linux kernel, the following vulnerability has been resolved:

net: mvneta: re-enable percpu interrupt on resume

On Marvell MPIC platforms (Armada 370/XP/38x), mvneta uses a percpu IRQ disable/enable scheme for NAPI: the ISR (mvnetapercpuisr) calls disablepercpuirq() to mask the MPIC per-CPU interrupt and schedules NAPI poll, which calls enablepercpuirq() on completion to unmask.

If suspend occurs while NAPI poll is pending (between disablepercpuirq in the ISR and enablepercpuirq in poll completion), the interrupt is never re-enabled:

1. mvnetapercpuisr: disablepercpuirq() + napischedule() => MPIC masked, percpuenabled cpumask bit cleared
2. NAPI poll does not complete before suspend proceeds (on PREEMPT_RT this is highly likely since softirqs run in ksoftirqd which gets frozen; on non-RT it can happen when softirq processing is deferred to ksoftirqd)
3. mvnetastopdev => napi_disable(): cancels the pending poll without executing the completion path
4. suspenddeviceirqs => IRQCHIPMASKONSUSPEND: masks MPIC (already masked, but records IRQSSUSPENDED)
5. Resume: mpicresume checks irqpercpuisenabled() => false (bit was cleared in step 1) => skips unmask
6. mvnetastartdev only restores device-level INTRNEWMASK, does not touch the MPIC per-CPU mask

Result: MPIC per-CPU interrupt stays masked permanently. The NIC generates interrupts (INTRNEWCAUSE != 0) but the CPU never receives them, causing complete loss of network connectivity.

Fix by calling oneachcpu(mvnetapercpuenable) in the resume path to unconditionally unmask the MPIC per-CPU interrupt regardless of pre-suspend state.